one-pll clock generator CY26114 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07098 rev. *a revised december 14, 2002 features benefits ? integrated phase-locked loop internal pll with up to 333 mhz internal operation low skew, low jitter, high accuracy outputs meets critical timing requirements in complex system designs 3.3v operation with 2.5 v output option enables application compatibility part number outputs input frequency output frequency range CY26114 4 25mhz crystal input 2 copies of 100mhz, 1 copy of 50mhz, 1 copy 25/33/50/66mhz (frequency selectable) clk4 frequency select options fs1 fs0 clk 4 units 00 25 mhz 01 33 mhz 10 50 mhz 11 66 mhz logic block diagram xin xout output multiplexer and dividers pll osc. 100mhz q p vco vddl avss avdd vss fs0 fs1 100mhz 50mhz 25/33/50/66mhz vssl vdd (frequency selectable) 16-pin tssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vss vssl fs1 xin xout vdd fs0 avss n/c clk4 clk3 avdd vddl n/c pin configurations lclk1 lclk2
CY26114 document #: 38-07098 rev. *a page 2 of 5 absolute maximum conditions recommended operating conditions pin definitions name pin number description xin 1 reference crystal input v dd 2 voltage supply av dd 3 analog voltage supply fs0 4 frequency select 0 av ss 5 analog ground v ssl 6 lclk ground lclk1 7 100-mhz output clock at v ddl level lclk2 8 100-mhz output clock at v ddl level n/c 9 no connect fs1 10 frequency select 1 v ddl 11 lclk voltage supply (2.5v or 3.3v) n/c 12 no connect vss 13 ground clk3 14 50-mhz output clock clk4 15 25/33/50/66-mhz clock output (frequency selectable) xout 16 reference crystal output parameter description min. max. unit v dd supply voltage ? 0.5 7.0 v v ddl i/o supply voltage 7.0 v t j junction temperature 125 c digital inputs av ss ? 0.3 av dd + 0.3 v digital outputs referred to v dd v ss ? 0.3 v dd + 0.3 v digital outputs referred to v ddl v ss ? 0.3 v ddl +0.3 v electro-static discharge 2 kv parameter description min. typ. max. unit v dd operating voltage 3.0 3.3 3.6 v v ddl operating voltage 2.375 2.5 2.625 v t a ambient temperature 0 70 c c load max. load capacitance 15 pf f ref reference frequency 25 mhz t pu power-up time for all vdd's to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms note: 1. float xout if xin is externally driven.
CY26114 document #: 38-07098 rev. *a page 3 of 5 dc electrical characteristics ac electrical characteristics parameter [2] name description min. typ. max. unit i oh output high current v oh = v dd ? 0.5, v dd /v ddl = 3.3v 12 24 ma i ol output low current v ol = 0.5, v dd /v ddl = 3.3v 12 24 ma i oh output high current v oh = v ddl ? 0.5, v ddl =2.5v 8 16 ma i ol output low current v ol = 0.5, v ddl = 2.5v 8 16 ma v ih input high voltage cmos levels, 70% of v dd 0.7 vdd v il input low voltage cmos levels, 30% of v dd 0.3 vdd i vdd supply current av dd /v dd current 25 ma i vddl supply current v ddl current (v ddl = 3.6v) 20 ma i vddl supply current v ddl current (v ddl = 2.625v) 15 ma parameter [2] name description min. typ. max. unit dc output duty cycle duty cycle is defined in figure 1; t1/t2, 50% of v dd 45 50 55 % t 3 rising edge rate output clock rise time, 20% ? 80% of v dd /v ddl = 3.3v 0.8 1.4 v/ns t 3 rising edge rate output clock rise time, 20% ? 80% of v ddl = 2.5v 0.6 1.2 v/ns t 4 falling edge rate output clock fall time, 80% ? 20% of v dd /v ddl = 3.3v 0.8 1.4 v/ns t 4 falling edge rate output clock fall time, 80% ? 20% of v ddl = 2.5v 0.6 1.2 v/ns t5 skew delay between related outputs at rising edge 250 ps t9 clock jitter peak to peak period jitter 200 ps t10 pll lock time 3ms figure 1. duty cycle definitions: dc = t2/t1. figure 2. rise time and fall time definitions. note: 2. not 100% tested. t1 t2 clk 50% 50% t3 clk 80% 20% t4
CY26114 document #: 38-07098 rev. *a page 4 of 5 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. test circuit ordering information ordering code package name package type operating range operating voltage CY26114zc z16 16-pin tssop commercial 3.3v 0.1 f v dd 0.1 f av dd clk out c load gnd outputs
CY26114 document #: 38-07098 rev. *a page 5 of 5 document title: CY26114 one-pll clock generator document number: 38-07098 rev. ecn no. issue date orig. of change description of change ** 107333 08/28/01 ckn new data sheet *a 121867 12/14/02 rbi power up requirements added to operating condi- tions information
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